The invention relates to a semiconductor device and, more particularly, to a semiconductor device having a recessed channel and a method of manufacturing the semiconductor device.
Higher degrees of integration of semiconductor devices and abrupt shrinkage of design rules have led to increased difficulties in ensuring reliable transistor operation. Particularly, in sub-50 nm semiconductor device design rules in which transistors are correspondingly small, limitations are imposed on cell threshold voltages (Vt) and refresh margins.
Accordingly, diverse methods for ensuring an effective channel length without increasing the design rule are being researched. One such method for effective channel length extension involves extending the length of a channel with respect to a restricted gate line width, embodied in a transistor including a recessed channel and a fin field effect transistor (FinFET) having a fin-shaped active region. However, double data rate 2 (DDR2) dynamic random access memory (DRAM) products currently being used are prone to drastic reductions in data retention time under high temperature test conditions, compared to earlier DDR DRAM products. Also, reduction in the width of an active region results in deterioration of operating voltage characteristics. Additionally, in contrast to conventional recessed gate transistors, because an isolation layer must be removed to below a recessed gate in a FinFET, word line thickness increases. Thickening of word lines greatly increases coupling capacitance between the respective word lines, causing a signal transfer delay on the word lines. Further, when a word line adjacent to an active region is turned on, an electric field is concentrated at the junction, increasing leakage current and degrading refresh characteristics.